Senior Design Verification Engineer

Capgemini - Europa, 🇺🇦 Ucrania, Kyiv

Own verification of IP’s and SoC’s in prototype and SoC design environment; Establish functional and performance benchmarks; Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms; IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.