Junior Dv And Fpga Prototyping Engineer

Capgemini - Europe, 🇺🇦 Ukraine, Kyiv

Your on-job tasks would consist of: - Studying AMD Vivado and Vitis IDE - Modelling (Python) and RTL implementation (System Verilog) of the proposed image and/or audio processing algorithms - Building FPGA environment and debug of the implemented RTL design using Zybo Z7 board - Building SV based verification environment for simple RTL designs like FIFO, UART. We’d expect you to learn: - OOP concepts in System Verilog (classes, inheritance, polymorphism) - Constrained randomization (rand variables, constraints, inline constraints, conflict solving) - Functional coverage (covergroups, coverpoints, cross coverage, bins) - Assertions (simple SVA properties checks) - Studying UVM methodology - Wrapping SV based environment into UVM - Shell and Python scripting