Senior Cad Semiconductor Engineer (eda Flow )

Capgemini - Europa, 🇺🇦 Ucrania, Odesa

Assumptions: This Job Description document is mainly for a Senior CAD Engineer / Technical Lead. Leadership expectations can be adjusted for more junior roles with increased hands-on focus. Mission Define, deploy, and maintain EDA tool flows and CAD infrastructure supporting semiconductor design and verification activities across full SoC lifecycle. Drive the evaluation, benchmarking, and integration of EDA tools (Cadence, Synopsys, Siemens EDA, Arteris) and associated flows to maximize productivity, reliability, and scalability. Own the engineering infrastructure environment (compute, storage, licensing, CI/CD, automation) required for advanced chip design workloads. Collaborate with design, verification, and physical implementation teams to ensure efficient, robust, and scalable tool usage. Explore and integrate AI/ML-based tooling and workflows to improve engineering productivity (automation, debugging, optimization, knowledge extraction). Ensure optimal trade-offs between performance, cost, scalability, and usability of the CAD environment. Act as a key technical interface between internal engineering teams, management, and EDA vendors. Provide regular reporting on tool performance, usage, and roadmap alignment.